Mr. Nguyen has prepared and prosecuted hundreds of patent applications mostly on semiconductor devices (design and fabrication) and electrical circuits.

More specifically, these applications are directed, but not limited, to: semiconductor transistors, diodes, light sensors, coupling capacitance reduction, heat sinks, trench capacitors, clock signals in digital circuits, phase-locked loops, voltage controlled oscillators, noise reduction in digital circuits, reduction of gate dielectric leakage current, wafer alignment, charge pumps, power distribution systems in digital circuits, data bus receivers, memory testing and repairing, resistors in semiconductor devices, vertical transistors, chip dicing, defect diagnosis for semiconductor integrated circuits, FinFET (Fin Field Effect Transistor), halo implants, STI (Shallow Trench Isolation) structures, reduction of out-fringing capacitance, data caching in internet content requests, optimization of network usage, UV tape removal in wafer processing, transistors with aligned dual gates, circuit design verification process, hybrid orientation semiconductor structures, flip-chip technologies, lithographic chemical shrink processes, wafer edge patterning, circuit design testing, sidewall image transfer (SIT) process, sidewall MOSFET, electric fuses using carbon nanotubes, damascene processes, back gate technology, digital image processing, optical proximity correction, epitaxial growth, ion implantation, efuses, through-wafer vias, localized metal precipitate/depletion, strained channel transistors, LDMOS (laterally diffused metal oxide semiconductor) technology, reduction of chip crack propagation, scan chain diagnostics, double exposure processes, resistor tuning, Multi-Gate FETs, parasitic capacitance, chip packaging process, well isolation trenches for CMOS devices, particle emission analysis for semiconductor fabrication, trench DRAM cells, voltage translator circuits, antenna, lithographic chemical shrink processes, cooling systems for ICs, reduction of electromigration effect, monitoring stress in solder balls in flip-chip technologies, balanced sense amplifier circuits, interposers in multi-chip integrated circuits, simulation of digital circuits, etching tools for dry etching, minimizing wiring congestion in logic design, semiconductor surface planarization methods, multiple bit memory cells, error detection and correction in semiconductor devices, local plasma deposition, thin film deposition chamber, laser fuses, memory hard failure repair during normal operation, stopping powers of design structures with respect to a traveling particle, demultiplexer circuits, strained HOT (Hybrid Orientation Technology) MOSFETs, alpha particle shields in chip packaging…



  1. US Patent # 7,088,190. Voltage-controlled oscillators having controlling circuits.
  2. US Patent # 7,012,316. Isolation structures in semiconductor integrated circuits (IC).
  3. US Patent # 7,397,081. Sidewall semiconductor transistors.


  • * Admitted to the State Bar of Texas.
  • * Registered to practice before the USPTO.
    J.D. in 1998.
    Magna cum laude.
  • * UNIVERSITY OF HOUSTON, Houston, Texas
    B.S. in Electrical Engineering in 1995.
    Summa cum laude.